About the Project
Diann is a functional verification tool I built as part of Instachip, a startup I worked on during and coming out of high school. Diann leverages large language models (LLMs) to automate and enhance the verification process for SystemVerilog designs. The tool uses AI to generate test cases for "spot checking" problem modules/behavior and analyze coverage.
By combining traditional verification methodologies with modern AI capabilities, Diann aims to significantly reduce the time and effort required for comprehensive hardware verification. The tool helps engineers catch bugs earlier in the design cycle and improves overall design quality through intelligent test generation and analysis.