About the Project
Openchips is an open-source library of Verilog and SystemVerilog modules designed to be a simple, centralized location for sharing and building on IP for use in projects. The repository was designed to be used with the Verilog Package Manager to make it easier to integrate open-source IP.
The project aims to create a comprehensive collection of digital design building blocks, from basic gates and arithmetic units to more complex peripherals and communication interfaces. The goal was to build a community, lower the barrier to entry for hardware design, and promote best practices in HDL coding.