About the Project
Verilog Project Manager (VPM) is a package management CLI tool for Verilog and SystemVerilog projects, inspired by modern software package managers like npm and pip (pip install modules!). It simplifies dependency management and project organization for hardware design.
VPM allows hardware engineers to easily integrate open source IP cores and design libraries into their projects. The tool has designed to handle basic version control, project configuration, headerfile generation, and compilation, making it easier to build complex digital systems from reusable components.
This was created as part of the Instachip startup.